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ltm4616 1 4616fd features a pplications description dual 8a per channel low v in dc/dc module regulator the lt m ? 4616 is a complete dual 2-phase 8 a per channel switch mode dc/dc power regulator system in a 15mm 15 mm surface mount lga or bga package. included in the package are the switching controller, power fets, inductor and all support components. operating from an input voltage range of 2.7 v to 5.5 v, the ltm4616 supports two outputs within a voltage range of 0.6 v to 5 v, each set by a single external resistor. this high efficiency design delivers up to 8 a continuous current (10 a peak) for each output. only bulk input and output capacitors are needed, depending on ripple requirement. the part can also be configured for a 2-phase single output at up to 16a. the low profile package enables utilization of unused space on the back side of pc boards for high density point-of- load regulation. fault protection features include overvoltage protection, overcurrent protection and thermal shutdown. the power module is offered in space saving and thermally enhanced 15mm 15mm 2.82 mm lga and 15mm 15mm 3.42mm bga packages. the ltm4616 is rohs compliant with pb-free finish. different combinations of input and output number of inputs number of outputs i out (max) 2 2 8a, 8a 2 1 16a 1 2 8a, 8a 1 1 16a dual output dc/dc module ? regulator n complete dual dc/dc regulator system n input voltage range: 2.7v to 5.5v n dual 8a outputs, or single 16a output with a 0.6v to 5v range n output voltage tracking and margining n 1.75% total dc output error (C 55c to 125c) n current mode control/fast transient response n power good tracking and margining n overcurrent/thermal shutdown protection n onboard frequency synchronization n spread spectrum frequency modulation n multiphase operation n selectable burst mode ? operation n output overvoltage protection n rohs compliant with pb-free finish, gold finish lga (e4) or sac 305 bga (e1) n small surface mount footprint, low profile (15mm 15mm 2.82mm) lga and (15mm 15mm 3.42mm) bga packages n telecom, networking and industrial equipment n storage and atca, pci express cards n battery operated equipment efficiency vs load current t ypical a pplication l, lt , lt c , lt m , linear technology, the linear logo, burst mode, module and polyphase are registered trademarks and ltpowercad is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131, 6724174. 3.09k 100f 10f v in2 3.3v to 5v v out2 2.5v/8a v in1 v in2 v out1 fb1 i thm1 v out2 fb2 i thm2 gnd1 gnd2 4616 ta01a ltm4616 2.21k 100f 10f v in1 5v v out1 3.3v/8a load current (a) 0 70 efficiency (%) 75 80 85 90 95 2 4 6 4616 ta01b 8 5v in 3.3v out 5v in 2.5v out
ltm4616 2 4616fd p in c on f iguration a bsolute maxi m u m r atings a bsolute maxi m u m r atings v in 1 , sv in 1 , v in 2 , sv in 2 ................................ C 0.3 v to 6v clkout 1, clkout 2 .................................... C 0. 3 v to 2v pgood 1, plllpf 1, clkin 1, phmode 1, mode 1, pgood2, plllpf 2, clkin 2, phmode 2, mode 2 ..................................... C 0. 3 v to v in i th 1 , i thm 1 , run 1, fb 1, track 1, mgn 1, bsel 1, i th 2 , i thm 2 , run 2, fb 2, track 2, mgn 2, bsel 2 ............................................. C 0. 3 v to v in v out 1 , v out 2 , sw 1, sw2 ............................ C 0. 3 v to v in internal operating temperature range ( note 2) e- and i- grades .................................. C 4 0 c to 125 c mp - grade .......................................... C 5 5 c to 125 c junction temperature ........................................... 12 5 c storage temperature range .................. C 5 5 c to 125 c (note 1)(note 1) lga package 144-lead (15mm 15mm 2.82mm) top view v in2 v out2 i th2 1 2 3 4 5 6 7 8 109 11 12 l k j h g f e d c b m a mode1 clkin1 phmode1 v out1 gnd2 gnd1 v in1 sv in1 sgnd2 run2 sgnd1 plllpf2 sw2 clkout2 sw1 clkin2 plllpf1 bsel2 run1 bsel1 sv in2 track1 i thm2 fb1 mode2 i thm1 clkout1 pgood1 track2 phmode2 i th1 mgn1 pgood2 mgn2 fb2 t jmax = 125c, ja = 10.5c/w, jcbottom = 2c/w, jctop = 16c/w, weight = 1.8g ja derived from 95mm 76mm pcb with 4 layers bga package 144-lead (15mm 15mm 3.42mm) top view v in2 v out2 i th2 1 2 3 4 5 6 7 8 109 11 12 l k j h g f e d c b m a mode1 clkin1 phmode1 v out1 gnd2 gnd1 v in1 sv in1 sgnd2 run2 sgnd1 plllpf2 sw2 clkout2 sw1 clkin2 plllpf1 bsel2 run1 bsel1 sv in2 track1 i thm2 fb1 mode2 i thm1 clkout1 pgood1 track2 phmode2 i th1 mgn1 pgood2 mgn2 fb2 t jmax = 125c, ja = 10.5c/w, jcbottom = 2c/w, jctop = 16c/w, weight = 2.0g ja derived from 95mm 76mm pcb with 4 layers lead free finish tray part marking* package description temperature range (note 2) ltm4616ev#pbf ltm4616ev#pbf ltm4616v 144-lead (15mm 15mm 2.82mm) lga C40c to 125c ltm4616iv#pbf ltm4616iv#pbf ltm4616v 144-lead (15mm 15mm 2.82mm) lga C40c to 125c ltm4616 mpv #pbf ltm4616 mpv #pbf ltm4616v 144-lead (15mm 15mm 2.82mm) lga C55c to 125c ltm4616ey#pbf ltm4616ey#pbf ltm4616y 144-lead (15mm 15mm 3.42mm) bga C40c to 125c ltm4616iy#pbf ltm4616iy#pbf ltm4616y 144-lead (15mm 15mm 3.42mm) bga C40c to 125c ltm4616 mpy #pbf ltm4616 mpy #pbf ltm4616y 144-lead (15mm 15mm 3.42mm) bga C55c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/ o r d er i n f or m ation
ltm4616 3 4616fd e lectrical c haracteristics the l denotes the specifications which apply over the specified internal operating temperature range (note 2). t a = 25c, v in = 5v unless otherwise noted. per the typical application in figure 18. specified as each channel (note 3). symbol parameter conditions min typ max units v in1(dc), v in2(dc) input dc voltage l 2.7 5.5 v v out1(dc) , v out2(dc) output voltage, total variation with line and load c in = 10f 1, c out = 100f ceramic, 100f poscap, r fb = 6.65k, mode = 0v v in = 2.7v to 5.5v, i out = i out(dc)min to i out(dc)max (note 4) l 1.472 1.464 1.49 1.49 1.508 1.516 v v input specifications v in1(uvlo) , v in2(uvlo) undervoltage lockout threshold sv in rising sv in falling 2.05 1.85 2.2 2.0 2.35 2.15 v v i q(vin1, vin2) input supply bias current v in = 3.3v, v out = 1.5v, no switching, mode = v in v in = 3.3v, v out = 1.5v, no switching, mode = 0v v in = 3.3v, v out = 1.5v, switching continuous 400 1.15 55 a ma ma v in = 5v, v out = 1.5v, no switching, mode = v in v in = 5v, v out = 1.5v, no switching, mode = 0v v in = 5v, v out = 1.5v, switching continuous 450 1.3 75 a ma ma shutdown, run = 0, v in = 5v 1 a i s(vin1, vin2) input supply current v in = 3.3v, v out = 1.5v, i out = 8a v in = 5v, v out = 1.5v, i out = 8a 4.5 2.93 a a output specifications i out1(dc), i out2(dc) output continuous current range (note 4) v out = 1.5v v in = 3.3v, 5.5v v in = 2.7v 0 0 8 5 a a v out1(line) /v out1 v out2(line) /v out2 line regulation accuracy v out = 1.5v, v in from 2.7v to 5.5v, i out = 0a l 0.1 0.25 %/v v out1(load) /v out1 v out2(load) /v out2 load regulation accuracy v out = 1.5v (note 4) v in = 3.3v, 5.5v, i load = 0a to 8a v in = 2.7v, i load = 0a to 5a l l 0.3 0.3 0.5 0.5 % % v out1(ac) , v out2(ac) output ripple voltage i out = 0a, c out = 100f x5r ceramic, v in = 5v, v out = 1.5v 10 mv p-p f s1, f s2 switching frequency i out = 8a, v in = 5v, v out = 1.5v 1.25 1.5 1.75 mhz f sync1, f sync2 sync capture range 0.75 2.25 mhz v out1(start), v out2(start) turn-on overshoot c out = 100f, v out = 1.5v, i out = 0a v in = 3.3v v in = 5v 10 10 mv mv t start1, t start2 turn-on time c out = 100f, v out = 1.5v, v in = 5v, i out = 1a resistive load, track = v in 100 s v out1(ls), v out2(ls) peak deviation for dynamic load load: 0% to 50% to 0% of full load, c out = 100f ceramic x2, 470f poscap, v in = 5v, v out = 1.5v 20 mv t settle1, t settle2 settling time for dynamic load step load: 0% to 50% to 0% of full load, v in = 5v, v out = 1.5v, c out = 100f 10 s i out1(pk), i out2(pk) output current limit c out = 100f v in = 2.7v, v out = 1.5v v in = 3.3v, v out = 1.5v v in = 5v, v out = 1.5v 8 11 13 a a a
ltm4616 4 4616fd efficiency vs load current e lectrical c haracteristics the l denotes the specifications which apply over the specified internal operating temperature range (note 2). t a = 25c, v in = 5v unless otherwise noted. per the typical application in figure 18. specified as each channel (note 3). symbol parameter conditions min typ max units control section fb1, fb2 voltage at fb pin i out = 0a, v out = 1.5v, v in = 2.7v to 5.5v l 0.590 0.587 0.596 0.596 0.602 0.606 v v ss delay internal soft-start delay 90 s i fb1 , i fb2 0.2 a v run1, v run2 run pin on/off threshold run rising run falling 1.4 1.3 1.55 1.4 1.7 1.5 v v track1, track2 tracking threshold (rising) tracking threshold (falling) tracking disable threshold run = v in run = 0v 0.57 0.18 v in C 0.5 v v v r fbhi1, r fbhi2 resistor between v out and fb pins 9.95 10 10.05 k v pgood1, v pgood2 pgood range 10 % %margining output voltage margining percentage mgn = v in , bsel = 0v mgn = v in , bsel = v in mgn = v in , bsel = float mgn = 0v, bsel = 0v mgn = 0v, bsel = v in mgn = 0v, bsel = float 4 9 14 C4 C9 C14 5 10 15 C5 C10 C15 6 11 16 C6 C11 C16 % % % % % % note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltm4616 is tested under pulsed load conditions, such that t j t a . the ltm4616e is guaranteed to meet performance specifications over the 0c to 125c internal operating temperature range. specifications over the C 40c to 125c internal operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltm4616i is guaranteed to meet specifications over the C40c to 125c internal operating temperature range. the ltm4616mp is guaranteed and tested over the C55c to 125c internal operating temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. note 3: tw o channels are tested separately and the same testing conditions are applied to each channel. note 4: see output current derating curves for different v in , v out and t a . efficiency vs load current efficiency vs load current load current 0 70 efficiency (%) 75 80 85 90 95 100 2 4 6 8 4616 g01 5v in 1.2v out 5v in 1.5v out 5v in 1.8v out 5v in 2.5v out 5v in 3.3v out continuous mode load current 0 70 efficiency (%) 75 80 85 90 95 100 2 4 6 8 4616 g02 3.3v in 1.2v out 3.3v in 1.5v out 3.3v in 1.8v out 3.3v in 2.5v out continuous mode load current (a) 0 efficiency (%) 90 95 100 2 4 5 4616 g03 80 70 85 75 1 3 6 7 2.7v in 1.0v out 2.7v in 1.5v out 2.7v in 1.8v out continuous mode t ypical p er f or m ance c haracteristics specified as each channel
ltm4616 5 4616fd v in (v) 2 v out (v) 1.5 2.0 2.5 3 5 4616 g06 1.0 0.5 0 4 3.0 3.5 4.0 6 i out = 6a v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v v in (v) 2 v out (v) 1.5 2.0 2.5 3 5 4616 g05 1.0 0.5 0 4 3.0 3.5 4.0 6 i out = 8a v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v t ypical p er f or m ance c haracteristics burst mode efficiency with 5v input v in to v out step-down ratio supply current vs v in load transient response load transient response v in to v out step-down ratio load current (a) 40 efficiency (%) 60 80 100 50 70 90 0.2 0.4 0.6 0.8 4616 g04 1.11.0 0.10 0.3 0.5 0.7 0.9 v out = 1.5v v out = 2.5v v out = 3.3v input voltage (v) 2.5 supply current (ma) 4.5 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 4616 g07 3.53 5 4 5.5 v o = 1.2v pulse-skipping mode v o = 1.2v burst mode operation 0a i load 1a/div v out 50mv/div 20s/div v in = 5v v out = 3.3v 2a /s step c out = 2 100f x5r, 470f 4v poscap 4616 g08 specified as each channel i load 1a/div v out 50mv/div 20s/div v in = 5v v out = 2.5v 2a/s step c out = 2 100f x5r, 470f 4v poscap 4616 g09 0a load transient response load transient response load transient response i load 1a/div v out 50mv/div 20s/div v in = 5v v out = 1.8v 2.5a/s step c out = 2 100f x5r, 470f 4v poscap 4616 g10 0a i load 1a/div v out 50mv/div 20s/div v in = 5v v out = 1.5v 2.5a/s step c out = 2 100f x5r, 470f 4v poscap 4616 g11 0a i load 1a/div v out 50mv/div 20s/div v in = 5v v out = 1.2v 2.5a/s step c out = 2 100f x5r, 470f poscap 4616 g12 0a
ltm4616 6 4616fd temperature (c) ?50 v fb (mv) 592 594 596 25 75 100 4616 g14 590 ?25 0 50 598 600 602 125 v in = 5.5v v in = 3.3v v in = 2.7v start-up v fb vs temperature load regulation vs current 2.5v output current short-circuit protection (2.5v short, no load) v out 0.5v/div v in 2v/div 50s/div v in = 5v v out = 1.5v c out = 100f no load and 8a load (default 100s soft-start) 4616 g13 load current (a) 0 ?0.6 load regulation (%) ?0.5 ?0.2 ?0.3 ?0.1 0 2 4 ?0.4 6 8 4616 g15 fc mode v in = 3.3v v out = 1.5v short-circuit protection (2.5v short, 4a load) output current (a) 0 0 output voltage (v) 0.5 1.0 1.5 2.0 2.5 3.0 5 10 15 20 4616 g16 2v/div 2v/div 5a/div 50s/div 4616 g17 v out v in i out v in = 5v v out = 2.5v 5v/div 5v/div 5a/div 50s/div 4616 g18 v out v in i out load v in = 5v v out = 2.5v t ypical p er f or m ance c haracteristics specified as each channel
ltm4616 7 4616fd plllpf1 and plllpf 2 ( e6 and l6): phase-locked loop lowpass filter for each channel. an internal lowpass filter is tied to this pin. in spread spectrum mode, placing a capacitor here to sgnd controls the slew rate from one frequency to the next. alternatively, floating this pin allows normal running frequency at 1.5 mhz, tying this pin to sv in forces the part to run at 1.33 times its normal frequency (2mhz), tying it to ground forces the frequency to run at 0.67 times its normal frequency (1mhz). phmode1 and phmode 2 ( a9 and g9): phase selector input for each channel. this pin determines the phase relationship between the internal oscillator and clkout. tie it high for 2- phase operation, tie it low for 3-phase operation, and float or tie it to v in /2 for 4- phase operation. mgn1 and mgn2 (a 10 and g 10): voltage margining pin for each channel. increases or decreases the output voltage by the amount specified by the bsel pin. to disable margining, tie the mgn pin to a voltage divider with 50 k resistors from v in to ground ( see figure 5). for margining, connect a voltage divider from v in to gnd with the center point connected to the mgn pin for the spe- cific channel. each resistor should be close to 50k . margin high is within 0.3 v of v in , and margin low is within 0.3 v of gnd. see the applications information section and figure 18 for margining control. the specified tri- state drivers are capable of the high and low requirements for margining. bsel1 and bsel 2 ( a6 and g6): margining bit select pin for each channel. tying bsel low selects 5% margin value, tying it high selects 10% margin value. floating it or tying it to v in /2 selects 15% margin value. track1 and track2 (e 8 and l 8): output voltage tracking pin for each channel. voltage tracking is enabled when the track voltage is below 0.57 v. if tracking is not desired, then connect the track pin to sv in . if track is not tied to sv in , then the track pins voltage needs to be below 0.18v before the chip shuts down even though run is v in1 , v in2 , (bank1 and bank 2); ( f1-f4, e1-e4, c1-c2, d1-d2) and ( j1-j2, k1-k2, l1-l4, m1-m4): power input pins. apply input voltage between these pins and gnd pins. recommend placing input decoupling capacitance directly between v in pins and gnd pins. v out1 , v out2 ( bank3 and bank6); ( d9-d12, e9-e12, f9-f12) and ( k9-k12, l9-l12, m9-m12): power output pins. apply output load between these pins and gnd pins. recommend placing output decoupling capacitance directly between these pins and gnd pins. see table 1. gnd1 and gnd 2 ( bank2 and bank 5); ( a1-a5, a12, b1- b5, b7-b12, c3-c12, d3-d7) and ( g1-g5, g12, h1-h5, h7-h12, j3-j12, k3-k7): power ground pins for both input and output returns. sv in1 and sv in2 ( e5 and l5): signal input voltage for each channel. this pin is internally connected to v in through a lowpass filter. sgnd1 and sgnd 2 ( f5 and m5): signal ground pin for each channel. return ground path for all analog and low power circuitry. tie a single connection to the output capacitor gnd in the application. see layout guidelines in figure 17. mode1 and mode 2 ( a8 and g8): mode select input for each channel. tying this pin high enables burst mode operation. tying this pin low enables forced continuous operation. floating this pin or tying it to v in /2 enables pulse-skipping operation. clkin1 and clkin 2 ( a7 and g7): external synchroniza- tion input to phase detector for each channel. this pin is internally terminated to sgnd with a 50 k resistor. the phase-locked loop will force the internal top power pmos turn on to be synchronized with the rising edge of the clkin signal. connect this pin to sv in to enable spread spectrum modulation. during external synchronization, make sure the plllpf pin is not tied to v in or gnd. p in functions
ltm4616 8 4616fd p in functions already low. do not float this pin. a resistor and capacitor can be applied to the track pin to increase the soft-start time of the regulator. track1 and track2 can be tied together for parallel operation and tracking. see the ap- plications information section. fb1 and fb 2 ( d8 and k8): the negative input of the error amplifier for each channel. internally, this pin is connected to v out with a 10 k precision resistor. different output voltages can be programmed with an additional resistor between fb and gnd pins. in polyphase ? operation, tying the fb pins together allows for parallel operation. see the applications information section for details. i th1 and i th2 (f8 and m8): current control threshold and error amplifier compensation point for each channel. the current comparator threshold increases with this control voltage. tie together in parallel operation. i thm1 and i thm2 (e7 and l7): negative input to the internal i th differential amplifier for each channel. tie this pin to sgnd for single phase operation on each channel. for polyphase operation, tie the masters i thm to sgnd while connecting all of the i thm pins together at the master. pgood1 and pgood 2 ( a11 and g11): output voltage power good indicator for each channel. open-drain logic output that is pulled to ground when the output voltage is not within 10% of the regulation point. power good is disabled during margining. run1 and run 2 ( f6 and m6): run control pin. a voltage above 1.7v will turn on the module. sw1 and sw 2 ( b6 and h6): switching node of each channel that is used for testing purposes. this can be connected to an electronically open circuit copper pad on the board for improved thermal performance. clkout1 and clkout 2 ( f7 and m7): output clock signal for polyphase operation. the phase of clkout is determined by the state of the phmode pin.
ltm4616 9 4616fd s i m pli f ie d b lock diagra m internal filter power control internal comp internal filter sv in1 track1 mgn1 bsel1 pgood1 mode1 run1 clkin1 clkout1 phmode1 plllpf1 sgnd1 i th1 i thm1 m1 10f c out1 10f 10f 10f c in1 v in1 3v to 5.5v v out1 1.5v 8a sw1 pgnd1 fb1 10k r set1 6.65k 4616 bd 0.22h m2 + + v out1 50k pgnd1 internal filter power control internal comp internal filter sv in2 track2 mgn2 bsel2 pgood2 mode2 run2 clkin2 clkout2 phmode2 plllpf2 sgnd2 pgnd1 pgnd2 i th2 i thm2 m3 10f c out2 10f 10f 10f c in2 v in2 3v to 5.5v v out2 1.2v 8a sw2 pgnd2 fb2 10k r set2 10k 0.22h m4 + + v out2 50k pgnd2 figure 1. simplified ltm4616 block diagram
ltm4616 10 4616fd si m pli f ie d block d iagra m symbol parameter conditions min typ max units c in1 c in2 external input capacitor requirement (v in1 = 2.7v to 5.5v, v out1 = 1.5v) (v in2 = 2.7v to 5.5v, v out2 = 2.5v) i out1 = 8a i out2 = 8a 22 22 f f c out1 c out2 external output capacitor requirement (v in1 = 2.7v to 5.5v, v out1 = 1.5v) (v in2 = 2.7v to 5.5v, v out2 = 2.5v) i out1 = 8a i out2 = 8a 100 100 f f table 1. decoupling requirements. t a = 25c, block diagram configuration. the ltm4616 is a dual-output standalone nonisolated switching mode dc/dc power supply. it can provide two 8a outputs with few external input and output capacitors. this module provides precisely regulated output voltages programmable via external resistors from 0.6v dc to 5v dc over 2.7 v to 5.5 v input voltages. the typical application schematic is shown in figure 18. the ltm4616 has integrated constant frequency current mode regulators and built-in power mosfet devices with fast switching speed. the typical switching frequency is 1.5mhz. for switching noise sensitive applications, it can be externally synchronized from 0.75 mhz to 2.25mhz. even spread spectrum switching can be implemented in the design to reduce noise. with current mode control and internal feedback loop compensation, the ltm4616 module has sufficient stabil- ity margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. current mode control provides cycle-by-cycle fast current limit and thermal shutdown in an overcurrent condition. internal overvoltage and undervoltage comparators pull the open-drain pgood output low if the output feedback voltage exits a 10% window around the regulation point. the power good pins are disabled during margining. pulling the run pins below 1.3 v forces the regulators into a shutdown state, by turning off both mosfets. the track pin is used for programming the output voltage ramp and voltage tracking during start-up. see the ap- plications information section. the ltm4616 is internally compensated to be stable over all operating conditions. table 3 provides a guideline for input and output capacitances for several operating conditions. ltpowercad? design tool is available for fine tuning transient and stability perfromance. the fb pin is used to program the output voltage with a single external resistor to ground. multiphase operation can be easily employed with the synchronization and phase mode controls. the ltm4616 has clock in and clock out for poly phasing multiple devices or frequency synchronization. high efficiency at light loads can be accomplished with selectable burst mode operation using the mode pin. these light load features will accommodate battery operation. efficiency graphs are provided for light load operation in the typical performance characteristics section. output voltage margining is supported, and can be pro- gramed from 5% to 15% using the mgn and bsel pins. o peration
ltm4616 11 4616fd a pplications i n f or m ation the typical ltm4616 application circuit is shown in figure 18. external component selection is primarily determined by the maximum load current and output voltage. refer to table 3 for specific external capacitor requirements for a particular application. v in to v out step-down ratios there are restrictions in the maximum v in to v out step- down ratio that can be achieved for a given input voltage. each output of the ltm4616 is capable of 100% duty cycle, but the v in to v out minimum drop out is still shown as a function of its load current. for a 5 v input voltage, both outputs can deliver 8 a for any output voltage. for a 3.3v input, all outputs can deliver 8 a, except 2.5v out and above which is limited to 6 a. all outputs derived from a 2.7v input voltage are limited to 5a. output voltage programming each pwm controller has an internal 0.596 v reference voltage. as shown in the block diagram, a 10 k internal feedback resistor connects v out and fb pins together. the output voltage will default to 0.596 v with no feed- back resistor. adding a resistor r fb from fb pin to gnd programs the output voltage: v out = 0.596v ? 10k + r fb r fb table 2. fb resistor vs various output voltages v out 0.596v 1.2v 1.5v 1.8v 2.5v 3.3v r fb open 10k 6.65k 4.87k 3.09k 2.21k for parallel operation of n number of outputs, the below equation can be used to solve for r fb . tie the fb pins together for each paralleled output with a single resistor to ground as determined by: r fb = 10k / n v out 0.596 ? 1 input capacitors the ltm4616 module should be connected to a low ac impedance dc source. for each regulator, three 10f ceramic capacitors are included inside the module. ad- ditional input capacitors are only needed if a large load step is required up to the 4 a level. a 47 f to 100f surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. this bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. if low impedance power planes are used, then this 47f capacitor is not needed. for a buck converter, the switching duty-cycle can be estimated as: d = v out v in without considering the inductor current ripple, the rms current of the input capacitor can be estimated as: i cin(rms) = i out(max) % ? d ? 1? d ( ) in the above equation, % is the estimated efficiency of the power module so the rms input current at the worst case for 8 a maximum current is about 4 a. the input bulk capacitor can be a switcher-rated aluminum electrolytic capacitor or polymer capacitor. each internal 10 f ceramic input capacitor is typically rated for 2 amps of rms ripple current. output capacitors the ltm4616 is designed for low output voltage ripple noise. the bulk output capacitors defined as c out are chosen with low enough effective series resistance (esr) to meet the output voltage ripple and transient require- ments. c out can be a low esr tantalum capacitor, low esr polymer capacitor or ceramic capacitor. the typical output capacitance range is from 47 f to 220f . additional output filtering may be required by the system designer, if further reduction of output ripple or dynamic transient spikes is desired. table 3 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 3 a/s transient. the table optimizes total equivalent esr and total bulk capacitance to optimize the transient performance. stability criteria are considered in the table 3 matrix. ltpowercad is available
ltm4616 12 4616fd a pplications i n f or m ation for those who wish to perform additional stability analysis. multiphase operation will reduce effective output ripple as a function of the number of phases. application note 77 discusses this noise reduction versus output ripple cur- rent cancellation, but the output capacitance will be more a function of stability and transient response. ltpowercad also calculates the output ripple reduction as the number of phases increases. burst mode operation the ltm4616 is capable of burst mode operation on each regulator in which the power mosfets operate intermit- tently based on load demand, thus saving quiescent current . for applications where maximizing the efficiency at very light loads is a high priority, burst mode operation should be applied. to enable burst mode operation, simply tie the mode pin to v in . during this operation, the peak current of the inductor is set to approximately 20% of the maximum table 3. output voltage response versus component matrix (refer to figure 18) 0a to 3a load step typical measured values c out1 vendors value part number c out2 vendors value part number tdk 22f, 6.3v c3216x7s0j226m sanyo poscap 470f, 4v 4tpe470m murata 22f, 16v grm31cr61c226k c in (bulk) vendors value part number tdk 100f, 6.3v c4532x5r0j107mz suncon 100f, 10v 10ce100fh murata 100f, 6.3v grm32er60j107m v out (v) c in (ceramic) c in (bulk)* c out1 (ceramic) c out2 (bulk) i th c1 c3 v in (v) droop (mv) peak-to- peak deviation (mv) recovery time (s) load step (a/s) r fb (k) 1.0 10f 100f 100f 2 470f none none none 5 20 40 40 2.5 14.7 1.0 10f 100f 100f 2 none none none 5 30 60 25 2.5 14.7 1.0 10f 100f 100f 2 none none none 2.7 30 60 25 2.5 14.7 1.0 10f 100f 22f 1 470f none none none 2.7 25 50 25 2.5 14.7 1.2 10f 100f 100f 2 none none none 5 20 40 25 2.5 10 1.2 10f 100f 22f 1 470f none none none 5 20 41 25 2.5 10 1.2 10f 100f 100f 2 none none none 2.7 30 60 20 2.5 10 1.2 10f 100f 22f 1 470f none none none 2.7 30 60 25 2.5 10 1.5 10f 100f 100f 2 none none none 5 32 64 20 2.5 6.65 1.5 10f 100f 22f 1 470f none none none 5 25 50 25 2.5 6.65 1.5 10f 100f 100f 1 none none none 3.3 22 42 25 2.5 6.65 1.5 10f 100f 22f 1 470f none none none 3.3 25 50 25 2.5 6.65 1.5 10f 100f 100f 2 none none none 2.7 30 60 25 2.5 6.65 1.5 10f 100f 22f 1 470f none none none 2.7 25 50 25 2.5 6.65 1.8 10f 100f 100f 1 none none none 5 42 80 25 2.5 4.87 1.8 10f 100f 22f 1 470f none none none 5 25 50 30 2.5 4.87 1.8 10 f 100f 100f 2 none none none 3.3 35 70 30 2.5 4.87 1.8 10f 100f 22f 1 470f none none none 3.3 25 50 30 2.5 4.87 1.8 10f 100f 100f 2 none none none 2.7 35 70 30 2.5 4.87 1.8 10f 100f 22f 1 470f none none none 2.7 35 20 30 2.5 4.87 2.5 10f 100f 100f 1 none none none 5 35 40 30 2.5 3.09 2.5 10f 100f 22f 1 470f none none none 5 32 65 40 2.5 3.09 2.5 10f 100f 100f 1 none none none 3.3 50 100 30 2.5 3.09 2.5 10f 100f 22f 1 470f none none none 3.3 32 65 40 2.5 3.09 3.3 10f 100f 100f 1 none none none 5 65 135 30 2.5 2.21 3.3 10f 100f 22f 1 470f none none none 5 40 87 40 2.5 2.21 *bulk capacitance is optional if v in has very low input impedance.
ltm4616 13 4616fd peak current value in normal operation even though the voltage at the i th pin indicates a lower value. the voltage at the i th pin drops when the inductors average current is greater than the load requirement. as the i th voltage drops below 0.2 v, the burst comparator trips, causing the internal sleep line to go high and turn off both power mosfets. in burst mode operation, the internal circuitry is partially turned off, reducing the quiescent current to about 450a for each output. the load current is now being supplied from the output capacitors. when the output voltage drops, causing i th to rise above 0.25 v, the internal sleep line goes low, and the ltm4616 resumes normal operation. the next oscillator cycle will turn on the top power mosfet and the switching cycle repeats. each regulator can be configured for burst mode operation. pulse-skipping mode operation in applications where low output ripple and high efficiency at intermediate currents are desired, pulse-skipping mode should be used. pulse -skipping operation allows the ltm4616 to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. floating the mode pin or tying it to v in /2 enables pulse-skipping operation. this allows discontinuous conduction mode ( dcm) opera - tion down to near the limit defined by the chips minimum on-time (about 100 ns). below this output current level, the converter will begin to skip cycles in order to main- tain output regulation. increasing the output load current slightly, above the minimum required for discontinuous conduction mode, allows constant frequency pwm . each regulator can be configured for pulse-skipping mode. forced continuous operation in applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. forced continuous operation can be enabled by tying the mode pin to gnd. in this mode, inductor cur- rent is allowed to reverse during low output loads, the i th a pplications i n f or m ation voltage is in control of the current comparator threshold throughout, and the top mosfet always turns on with each oscillator pulse. during start- up, forced continuous mode is disabled and inductor current is prevented from reversing until the ltm4616s output voltage is in regulation. each regulator can be configured for forced continuous mode. multiphase operation for output loads that demand more than 8 a of current, two outputs in ltm4616 or even multiple ltm4616s can be cascaded to run out-of-phase to provide more output current without increasing input and output voltage ripple. the clkin pin allows the ltc4616 to synchronize to an external clock (between 0.75 mhz and 2.25 mhz) and the internal phase-locked loop allows the ltm4616 to lock onto clkins phase as well. the clkout signal can be connected to the clkin pin of the following ltm4616 stage to line up both the frequency and the phase of the entire system. tying the phmode pin to sv in , sgnd or sv in /2 ( floating) generates a phase difference (between clkin and clkout) of 180, 120 or 90 respectively, which corresponds to a 2-phase, 3- phase or 4-phase operation. for a 6- phase example in figure 2, the 2nd stage that is 120 out-of-phase from the 1 st stage can generate a 240 (phmode = 0) clkout signal for the 3rd stage, which then can generate a clkout signal thats 420, or 60 (phmode = sv in ) for the 4 th stage. with the 60 clkin input, the next two stages can shift 120 (phmode?=?0) for each to generate a 300 signal for the 6th stage. finally, the signal with a 60 phase shift on the 6th stage ( phmode is floating) goes back to the 1 st stage. figure 3 shows the configuration for 12- phase operation. a multiphase power supply significantly reduces the amount of ripple current in both the input and output capacitors. the rms input ripple current is reduced by, and the effective ripple frequency is multiplied by, the number of phases used ( assuming that the input voltage is greater than the number of phases used times the output voltage). the output ripple amplitude is also reduced by the number of phases used.
ltm4616 14 4616fd a pplications i n f or m ation figure 2. 6-phase operation figure 3. 12-phase operation 4616 f02 0 +120 phase 1 clkout clkin phmode 120 phase 3 clkout clkin phmode 240 +180 +120 phase 5 clkout clkin phmode s vin (420) 60 phase 2 clkout clkin phmode +120 180 phase 4 clkout clkin phmode +120 300 phase 6 clkout clkin phmode 4616 f03 0 +120 phase 1 clkout clkin phmode 120 phase 5 clkout clkin phmode 240 +180 +120 phase 9 clkout clkin phmode s vin (420) 60 phase 3 clkout clkin phmode +120 180 phase 7 clkout clkin phmode +120 300 phase 11 clkout clkin phmode out2 out1 v in 90 +120 phase 4 clkout clkin phmode 210 phase 8 clkout clkin phmode 330 +180 +120 phase 12 clkout clkin phmode s vin (510) 150 (390) 30 phase 6 clkout clkin phmode +120 270 phase 10 clkout clkin phmode +120 phase 2 clkout clkin phmode ltc6908-2 the ltm4616 device is an inherently current mode con- trolled device, so parallel modules will have very good cur- rent sharing. this will balance the thermals on the design. tie the i th pins of each ltm4616 together to share the current. current sharing is inherently guaranteed by the current mode operation of the ltm4616s dc/dc regula- tors. moreover, the accuracy of current sharing between the two outputs is approximately 15%. to reduce ground potential noise, tie the i thm pins of all ltm4616s together and then connect to the sgnd of the master at the point it connects to the output capacitor gnd. see layout guideline in figure 17. figure 19 shows a schematic of the parallel design. the fb pins of the parallel module are tied together. input rms ripple current cancellation application note 77 provides a detailed explanation of multiphase operation. the input rms ripple current can- cellation mathematical derivations are presented, and a graph is displayed representing the rms ripple current reduction as a function of the number of interleaved phases. figure 4 shows this graph.
ltm4616 15 4616fd a pplications i n f or m ation spread spectrum operation switching regulators can be particularly troublesome where electromagnetic interference (emi) is concerned. switching regulators operate on a cycle-by-cycle basis to transfer power to an output. in most cases, the frequency of operation is fixed based on the output load. this method of conversion creates large components of noise at the frequency of operation ( fundamental) and multiples of the operating frequency (harmonics). to reduce this noise, the ltm4616 can run in spread spectrum operation by tying the clkin pin to sv in . in spread spectrum operation, the ltm4616s internal oscillator is designed to produce a clock pulse whose period is random on a cycle-by-cycle basis but fixed between 70% and 130% of the nominal frequency. this has the benefit of spreading the switching noise over a range of frequencies, thus significantly reducing the peak noise. spread spectrum operation is disabled if clkin is tied to ground or if its driven by an external frequency synchronization signal. a capacitor value of 0.01 f to 0.1f be placed from the plllpf pin to ground to control the slew rate of the spread spectrum frequency change. to ensure proper start-up, add a control ramp on the track pin with a resistor, r sr , from track to sv in and a capacitor, c sr , from track to ground: r sr 1 ? in 1? 0.592 v in ? ? ? ? ? ? ? 500 ? c sr ? ? ? ? ? ? ? ? duty factor (v o /v in ) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 4616 f04 rms input ripple current dc load current 6-phase 4-phase 3-phase 2-phase 1-phase figure 4. normalized input rms ripple current vs duty factor for one to six channels (phases)
ltm4616 16 4616fd a pplications i n f or m ation output voltage tracking output voltage tracking can be programmed externally using the track pin. the output can be tracked up and down with another regulator. the master regulator s output is divided down with an external resistor divider that is the same as the slave regulator s feedback divider to implement coincident tracking. the ltm4616 uses an accurate 10k resistor internally for the top feedback resistor. figure 5 shows an example of coincident tracking: slave = 1 + 10k r ta ? ? ? ? ? ? ? v track v track is the track ramp applied to the slaves track pin. v track has a control range of 0 v to 0.596 v, or the internal reference voltage. when the masters output is divided figure 5. dual outputs (3.3v and 1.5v) with tracking down with the same resistor values used to set the slaves output, then the slave will coincident track with the master until it reaches its final value. the master will continue to its final value from the slaves regulation point. voltage track- ing is disabled when v track is more than 0.596 v. r ta in figure 5 will be equal to r fb for coincident tracking. the track pin of the master can be controlled by an external ramp or by r sr and c sr in figure 5 referenced to v in . the rc ramp time can be programmed using equation: t = ? ln 1? 0.596v v in ? ? ? ? ? ? ? r sr ? c sr ? ? ? ? ? ? ratiometric tracking can be achieved by a few simple calculations and the slew rate value applied to the mas- ters track pin. as mentioned above, the track pin has r fb2 6.65k 10f 100f 100f 50k 50k slave 1.5v/8a v in1 sv in1 run1 plllpf1 mode1 phmode1 track1 v in2 sv in2 run2 plllpf2 mode2 phmode2 track2 v out1 fb1 i th1 i thm1 pgood1 bsel1 mgn1 v out2 fb2 i th2 i thm2 pgood2 bsel2 mgn2 sw1 clkin1 clkout1 clkin2 clkout2 sw2 sgnd1 gnd1 sgnd2 gnd2 clkin1 4616 f05 ltm4616 r fb1 2.21k 10f pgood bsel v in 4v to 5.5v master 3.3v/7a run run r tb 10k r ta 6.65k master 3.3v c sr r sr for track1: 1. tie to vin to disable track with default 100s soft start 2. apply a control ramp with r sr and c sr tied to v in with t = ?(ln(1?0.596/v in ) ? r sr ? c sr )) 3. apply an external tracking ramp directly 100f v in
ltm4616 17 4616fd a pplications i n f or m ation output voltage (v) time master output slave output 4616 f06 figure 6. output voltage coincident tracking a control range from 0 v to 0.596 v. the masters track pin slew rate is directly equal to the masters output slew rate in volts/time: mr sr ? 10k = r tb where mr is the masters output slew rate and sr is the slaves output slew rate in volts/time. when coincident tracking is desired, then mr and sr are equal, thus r tb is equal to 10k. r ta is derived from equation: r ta = 0.596v v fb 10k + v fb r fb ? v track r tb where v fb is the feedback voltage reference of the regula- tor and v track is 0.596 v. since r tb is equal to the 10k top feedback resistor of the slave regulator in coincident tracking, then r ta is equal to r fb2 with v fb = v track . therefore r tb = 10 k and r ta = 6.65 k in figure 5. figure ?6 shows the output voltage for coincident tracking. for applications that do not require tracking or sequencing, simply tie the track pin to sv in to let run control the turn on/off. connecting track to sv in also enables the ~100s of internal soft-start during start-up. power good the pgood pin is an open-drain pin that can be used to monitor valid output voltage regulation. this pin monitors a 10% window around the regulation point. as shown in figure 20, the sequencing function can be realized in a dual output application by controlling the run pins and the pgood signals from each other. the 1.5 v output begins its soft starting after the pgood signal of 3.3 v output becomes high, and 3.3 v output starts its shutdown after the pgood signal of 1.5 v output becomes low. this can be applied to systems that require voltage sequencing between the core and sub-power supplies. stability compensation the module has already been internally compensated for all output voltages. table 2 is provided for most ap- plication requirements. ltpowercad is available for fine adjustments to the control loop. output margining for a convenient system stress test on the ltm4616s output, the user can program each output to 5%, 10% or 15% of its normal operational voltage. margining can be disabled by connecting the mgn pin to a voltage divider as shown in figure 5. when the mgn pin is <0.3v, it forces negative margining, in which the output voltage is below the regulation point. when mgn is > v in C 0.3 v, the output voltage is forced above the regulation point. the mgn pin with a voltage divider is driven with a small tri-state gate as shown in figure 18 for three margin states, (high, low, and no margin). the amount of output voltage margining is determined by the bsel pin. when bsel is low, its 5%. when bsel is high, its 10%. when bsel is floating, its 15%. when margining is active, the internal output overvoltage and undervoltage comparators are disabled and pgood remains high. in ratiometric tracking, a different slew rate maybe desired for the slave regulator. r tb can be solved for when sr is slower than mr. make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach it final value before the master output. for example: mr = 3.3 v/ms and sr = 1.5 v/ms. then r tb = 22.1k. solve for r ta to equal to 4.87k.
ltm4616 18 4616fd a pplications i n f or m ation thermal considerations and output current derating the power loss curves in figures 7 and 8 can be used in coordination with the load current derating curves in figures 9 to16 for calculating an approximate ja thermal resistance for the ltm4616 with various heat sinking and airflow conditions. both ltm4616 outputs are placed in parallel for a total output current of 16 a, and the power loss curves are plotted for specific output voltages up to 16a. the derating curves are plotted with each output at 8a combined for a total of 16 a. the output voltages are 1.2v , 2.5 v and 3.3 v. these are chosen to include the lower and higher output voltage ranges for correlating the ther- mal resistance. thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. the junc- tion temperatures are monitored while ambient temperature increases with and without airflow. the junctions are maintained at ~115 c while lowering output current or power with increasing ambient temperature. the 115c value is chosen to allow for 10 c of margin relative to the maximum temperature of 125c . the decreased output cur - rent will decrease the internal module loss as ambient tem- perature is increased . the power loss curves in figures 7 and 8 show this amount of power loss as a function of load current that is specified with both channels in paral- lel. the monitored junction temperature of 115 c minus the ambient operating temperature specifies how much module temperature rise can be allowed. as an example, in figure 10 the load current is derated to 10 a at ~ 80 c and the power loss for the 5 v to 1.2 v at 10 a output is ~3.2 w. if the 80 c ambient temperature is subtracted from the 115c maximum junction temperature, then difference of 35c divided by 3.2 w equals a 10.9 c/w. table 4 specifies a 10.5 c/w value which is very close. table 4 and table 5 provide equivalent thermal resistances for 1.2 v and 3.3 v outputs, with and without airflow and heat sinking. the printed circuit board is a 1.6 mm thick four layer board with two ounce copper for the two outer layers and one ounce copper for the two inner layers. the pcb dimensions are 95mm 76 mm. the bga heat sinks are listed below table 5. at load currents on each channel from 3 a to 8a (6a to16a in parallel on the derating curves), the thermal resistance values in tables 4 and 5 are fairly accurate. as the load currents go below the 3 a level on each channel the thermal resistance starts to increase due to the reduced power loss on the board. the approximate thermal resis- tance values for these lower currents is 15c/w. safety considerations the ltm4616 modules do not provide isolation from v in to v out . there is no internal fuse. if required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. the device does support thermal shutdown and overcurrent protection. figure 7. 1.2v, 2.5v power loss figure 8. 1.2v, 3.3v power loss load current (a) 0 power loss (w) 4 5 6 16 4616 f07 3 2 0 4 8 12 1 8 7 3.3v in 1.2v out 3.3v in 2.5v out load current (a) 0 power loss (w) 4 5 6 16 4616 f08 3 2 0 4 8 12 1 8 7 5v in 1.2v out 5v in 3.3v out
ltm4616 19 4616fd a pplications i n f or m ation figure 9. 5v in to 3.3v out with no heat sink figure 10. 5v in to 1.2v out with no heat sink figure 11. 5v in to 3.3v out with bga heat sink figure 12. 5v in to 1.2v out with bga heat sink figure 13. 3.3v in to 1.2v out with no heat sink figure 14. 3.3v in to 2.5v out with no heat sink ambient temperature (c) 25 load current (a) 8 10 12 115 4616 f09 6 4 0 40 857055 100 2 16 14 0 lfm 200 lfm 400 lfm ambient temperature (c) 40 load current (a) 8 10 12 110 4616 f10 6 4 0 50 807060 90 100 2 16 14 0 lfm 200 lfm 400 lfm ambient temperature (c) 25 load current (a) 8 10 12 115 4616 f11 6 4 0 40 857055 100 2 16 14 0 lfm 200 lfm 400 lfm ambient temperature (c) 40 load current (a) 8 10 12 110 4616 f12 6 4 0 50 807060 90 100 2 16 14 0 lfm 200 lfm 400 lfm ambient temperature (c) 40 load current (a) 8 10 12 120 4616 f13 6 4 0 60 80 100 2 16 14 0 lfm 200 lfm 400 lfm ambient temperature (c) 30 load current (a) 8 10 12 110 4616 f14 6 4 0 90 70 50 2 16 14 0 lfm 200 lfm 400 lfm figure 15. 3.3v in 1.2v out with bga heat sink figure 16. 3.3v in 2.5v out with bga heat sink ambient temperature (c) 40 load current (a) 8 10 12 120 4616 f15 6 4 0 90 100 110 70 80 50 60 2 16 14 0 lfm 200 lfm 400 lfm ambient temperature (c) 30 load current (a) 8 10 12 110 4616 f16 6 4 0 90 70 50 2 16 14 0 lfm 200 lfm 400 lfm
ltm4616 20 4616fd a pplications i n f or m ation table 4. 1.2v output derating curve v in (v) power loss curve air flow (lfm) heat sink ja (c/w) figures 10, 13 3.3, 5 figures 7, 8 0 none 10.5 figures 10, 13 3.3, 5 figures 7, 8 200 none 8.0 figures 10, 13 3.3, 5 figures 7, 8 400 none 7.0 figures 12, 15 3.3, 5 figures 7, 8 0 bga heat sink 9.5 figures 12, 15 3.3, 5 figures 7, 8 200 bga heat sink 6.3 figures 12, 15 3.3, 5 figures 7, 8 400 bga heat sink 5.2 table 5. 3.3v output derating curve v in (v) power loss curve air flow (lfm) heat sink ja (c/w) figure 9 5 figure 8 0 none 10.5 figure 9 5 figure 8 200 none 8.0 figure 9 5 figure 8 400 none 7.0 figure 11 5 figure 8 0 bga heat sink 9.8 figure 11 5 figure 8 200 bga heat sink 7.0 figure 11 5 figure 8 400 bga heat sink 5.5 heat sink manufacturer part number website aavid thermalloy 375424b00034g www.aavidthermalloy.com cool innovations 4-050503p to 4-050508p www.coolinnovations.com
ltm4616 21 4616fd a pplications i n f or m ation figure 17. recommended pcb layout (lga and bga pcb layouts are identical with the exception of circle pads for bga. see package description.) layout checklist/example the high integration of ltm4616 makes the pcb board layout very simple and easy. however, to optimize its electrical and thermal performance, some layout con- siderations are still necessary. ? use large pcb copper areas for high current paths, including v in1 , v in2 , gnd1 and gnd2, v out1 and v out2 . it helps to minimize the pcb conduction loss and thermal stress. ? place high frequency ceramic input and output capaci- tors next to the v in , gnd and v out pins to minimize high frequency noise. ? place a dedicated power ground layer underneath the unit. ? to minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. ? do not put vias directly on the pads, unless they are capped or plated over. ? use a separated sgnd ground copper area for com- ponents connected to signal pins. connect the sgnd to gnd underneath the unit. ? for parallel modules, tie the i th , fb and i thm pins to- gether. use an internal layer to closely connect these pins together. all of the i thm pins connect to the sgnd of the master regulator, then the master sgnd connects to gnd. figure 17 gives a good example of the recommended layout. ltm4616 top view v in1 v out1 1 2 3 4 5 6 7 8 109 11 12 l k j h g f e d c b m a 4616 f17 gnd2 gnd2 gnd2 v out1 v out2 gnd1 gnd1 gnd2 v in1 v in2 c in1 c in2 c out2 c out2 via to gnd each channel control1 control1 & 2 control2
ltm4616 22 4616fd figure 18. typical 3v to 5.5v in , to 1.8v, 1.5v outputs a pplications i n f or m ation 6.65k 100f 2 10f v in2 3v to 5.5v v out2 1.5v/8a v in1 sv in1 run1 plllpf1 mode1 phmode1 track1 v in2 sv in2 run2 plllpf2 mode2 phmode2 track2 v out1 fb1 i th1 i thm1 pgood1 bsel1 mgn1 v out2 fb2 i th2 i thm2 pgood2 bsel2 mgn2 sw1 clkin1 clkout1 clkin2 clkout2 sw2 sgnd1 gnd1 sgnd2 gnd2 clkin1 4616 f18 ltm4616 4.87k 100f 10f pgood bsel pgood bsel v in1 3v to 5.5v v out1 1.8v/8a r3 50k r1 50k + ? r4 50k out gnd a2 v + i oe i in + ? r2 50k out gnd a1 v + i oe i in 5 pin sc70 package 5 pin sc70 package v in bsel: high = 10% float = 15% low = 5% a1, a2 pericom pi74st1g126cex toshiba tc7sz126afe oe in out mgn margin value h h l h l x h l z h l v in /2 + value of bsel selection ? value of bsel selection no margin v in
ltm4616 23 4616fd a pplications i n f or m ation figure 19. ltm4616 tw o outputs parallel, 1.5v at 16a design figure 20. ltm4616 output sequencing application 100f 100f 10f v in1 sv in1 run1 plllpf1 mode1 phmode1 track1 v in2 sv in2 run2 plllpf2 mode2 phmode2 track2 v out1 fb1 i th1 i thm1 pgood1 bsel1 mgn1 v out2 fb2 i th2 i thm2 pgood2 bsel2 mgn2 sw1 clkin1 clkout1 clkin2 clkout2 sw2 sgnd1 gnd1 sgnd2 gnd2 4616 f19 ltm4616 3.32k 100f 10f v in 3v to 5.5v v out 1.5v/16a run enable 50k 50k v in 100f v in1 sv in1 run1 plllpf1 mode1 phmode1 track1 v in2 sv in2 run2 plllpf2 mode2 phmode2 track2 v out1 fb1 i th1 i thm1 pgood1 bsel1 mgn1 v out2 fb2 i th2 i thm2 pgood2 bsel2 mgn2 sw1 clkin1 clkin clkout1 clkin2 clkout2 sw2 sgnd1 gnd1 sgnd2 gnd2 4616 f20 ltm4616 2.21k 6.65k 100f 22f v in 5v v out1 3.3v/7a v out2 1.5v/8a 100f shdnb pgood2 100k pgood1 100k 100k 50k 50k sv in1 100k sv in2 shdnb 3.3v 1.5v v in
ltm4616 24 4616fd a pplications i n f or m ation figure 21. four phase in parallel, 1.2v at 32a v in1 sv in1 run1 plllpf1 mode1 phmode1 track1 v in2 sv in2 run2 plllpf2 mode2 phmode2 track2 v out1 fb1 i th1 i thm1 pgood1 bsel1 mgn1 v out2 fb2 i th2 i thm2 pgood2 bsel2 mgn2 sw1 clkin1 clkout1 clkin2 clkout2 sw2 sgnd1 gnd1 sgnd2 gnd2 4616 f21 ltm4616 2.47k c1 470f 6.3v 10f 6.3v 10f 6.3v 10f 6.3v 10f 6.3v v in 3v to 5.5v v out 1.2v at 32a track input or v in v in1 sv in1 run1 plllpf1 mode1 phmode1 track1 v in2 sv in2 run2 plllpf2 mode2 phmode2 track2 v out1 fb1 i th1 i thm1 pgood1 bsel1 mgn1 v out2 fb2 i th2 i thm2 pgood2 bsel2 mgn2 sw1 clkin1 clkout1 clkin2 clkout2 sw2 sgnd1 gnd1 sgnd2 gnd2 ltm4616 + c2 470f 6.3v + sanyo poscap 10m c3 470f 6.3v + c4 22f 6.3v + c5 22f 6.3v + + ? r2 50k r1 50k a1 v + i oe i in out gnd v in 3v to 5.5v bsel: high = 10% float = 15% low = 5% a1, a2 pericom pi74st1g126cex toshiba tc7sz126afe oe in out mgn margin value h h l h l x h l z h l v in /2 + value of bsel selection ? value of bsel selection no margin optional margining circuit, if not used tie the mgn pins to a voltage equal to half of the respective v in 6 pin sc70 package
ltm4616 25 4616fd a pplications i n f or m ation figure 22. 4-phase, four outputs (3.3v, 2.5v, 1.8v and 1.5v) with tracking v in1 sv in1 run1 plllpf1 mode1 phmode1 track1 v in2 sv in2 run2 plllpf2 mode2 phmode2 track2 v out1 fb1 i th1 i thm1 pgood1 bsel1 mgn1 v out2 fb2 i th2 i thm2 pgood2 bsel2 mgn2 sw1 clkin1 clkout1 clkin2 clkout2 sw2 sgnd1 gnd1 sgnd2 gnd2 4616 f22 ltm4616 2.21k 100f 10f 10f 10f 10f v in 4v to 5.5v v out1 3.3v/7a v out2 2.5v/8a run enable v in1 sv in1 run1 plllpf1 mode1 phmode1 track1 v in2 sv in2 run2 plllpf2 mode2 phmode2 track2 v out1 fb1 i th1 i thm1 pgood1 bsel1 mgn1 v out2 fb2 i th2 i thm2 pgood2 bsel2 mgn2 sw1 clkin1 clkout1 clkin2 clkout2 sw2 sgnd1 gnd1 sgnd2 gnd2 ltm4616 3.3v 10k 3.16k 3.3v 10k 4.99k 3.3v 10k 6.65k 3.16k 4.99k 100f v out3 1.8v/8a 100f 100f 100f 6.65k v out4 1.5v/8a 100f v in 50k 50k
ltm4616 26 4616fd p ackage description pin assignment table (arranged by pin number) pin name pin name pin name pin name pin name pin name a1 gnd1 b1 gnd1 c1 v in1 d1 v in1 e1 v in1 f1 v in1 a2 gnd1 b2 gnd1 c2 v in1 d2 v in1 e2 v in1 f2 v in1 a3 gnd1 b3 gnd1 c3 gnd1 d3 gnd1 e3 v in1 f3 v in1 a4 gnd1 b4 gnd1 c4 gnd1 d4 gnd1 e4 v in1 f4 v in1 a5 gnd1 b5 gnd1 c5 gnd1 d5 gnd1 e5 sv in1 f5 sgnd1 a6 bsel1 b6 sw1 c6 gnd1 d6 gnd1 e6 plllpf1 f6 run1 a7 clkin1 b7 gnd1 c7 gnd1 d7 gnd1 e7 i thm1 f7 clkout1 a8 mode1 b8 gnd1 c8 gnd1 d8 fb1 e8 track1 f8 i th1 a9 phmode1 b9 gnd1 c9 gnd1 d9 v out1 e9 v out1 f9 v out1 a10 mgn1 b10 gnd1 c10 gnd1 d10 v out1 e10 v out1 f10 v out1 a11 pgood1 b11 gnd1 c11 gnd1 d11 v out1 e11 v out1 f11 v out1 a12 gnd1 b12 gnd1 c12 gnd1 d12 v out1 e12 v out1 f12 v out1 pin name pin name pin name pin name pin name pin name g1 gnd2 h1 gnd2 j1 v in2 k1 v in2 l1 v in2 m1 v in2 g2 gnd2 h2 gnd2 j2 v in2 k2 v in2 l2 v in2 m2 v in2 g3 gnd2 h3 gnd2 j3 gnd2 k3 gnd2 l3 v in2 m3 v in2 g4 gnd2 h4 gnd2 j4 gnd2 k4 gnd2 l4 v in2 m4 v in2 g5 gnd2 h5 gnd2 j5 gnd2 k5 gnd2 l5 sv in2 m5 sgnd2 g6 bsel2 h6 sw2 j6 gnd2 k6 gnd2 l6 plllpf2 m6 run2 g7 clkin2 h7 gnd2 j7 gnd2 k7 gnd2 l7 i thm2 m7 clkout2 g8 mode2 h8 gnd2 j8 gnd2 k8 fb2 l8 track2 m8 i th2 g9 phmode2 h9 gnd2 j9 gnd2 k9 v out2 l9 v out2 m9 v out2 g10 mgn2 h10 gnd2 j10 gnd2 k10 v out2 l10 v out2 m10 v out2 g11 pgood2 h11 gnd2 j11 gnd2 k11 v out2 l11 v out2 m11 v out2 g12 gnd2 h12 gnd2 j12 gnd2 k12 v out2 l12 v out2 m12 v out2
ltm4616 27 4616fd p ackage description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 5. primary datum -z- is seating plane 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature package top view 4 pin ?a1? corner x y aaa z aaa z package bottom view 3 see notes suggested pcb layout top view lga 144 1111 rev b ltmxxxxxx module tray pin 1 bevel package in tray loading orientation component pin ?a1? 0.0000 0.0000 d e b e e b f g lga package 144-lead (15mm 15mm 2.82mm) (reference ltc dwg # 05-08-1816 rev b) 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 6.9850 detail b package side view bbb z symbol a b d e e f g h1 h2 aaa bbb eee min 2.72 0.60 0.27 2.45 nom 2.82 0.63 15.00 15.00 1.27 13.97 13.97 0.32 2.50 max 2.92 0.66 0.37 2.55 0.15 0.10 0.05 notes dimensions total number of lga pads: 144 detail b substrate mold cap z h2 h1 a dia 0.630 pad 1 3x, c (0.22 x45) detail a 0.630 0.025 sq. 143x s yxeee detail a f g h m l j k e a b c d 2 1 4 3 567 12 891011
ltm4616 28 4616fd p ackage description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 5. primary datum -z- is seating plane 6. solder ball composition is 96.5% sn/3.0% ag/0.5% cu 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature package top view 4 pin ?a1? corner x y aaa z aaa z package bottom view pin 1 3 see notes suggested pcb layout top view bga 144 1011 rev a ltmxxxxxx module tray pin 1 bevel package in tray loading orientation component pin ?a1? detail a 0.0000 0.0000 detail a ?b (144 places) detail b substrate 0.27 ? 0.37 2.45 ? 2.55 // bbb z d a a1 b1 ccc z detail b package side view mold cap z m x yzddd m zeee 0.630 0.025 ? 144x symbol a a1 a2 b b1 d e e f g aaa bbb ccc ddd eee min 3.22 0.50 2.72 0.60 0.60 nom 3.42 0.60 2.82 0.75 0.63 15.0 15.0 1.27 13.97 13.97 max 3.62 0.70 2.92 0.90 0.66 0.15 0.10 0.20 0.30 0.15 notes dimensions total number of balls: 144 e b e e b a2 f g bga package 144-lead (15mm 15mm 3.42mm) (reference ltc dwg # 05-08-1902 rev a) 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 6.9850 f g h m l j k e a b c d 2 1 4 3 567 12 891011
ltm4616 29 4616fd information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h istory rev date description page number c 2/11 updated features updated pin configuration updated electrical characteristics replaced graphs g05 and g06 updated graph g18 updated pin functions updated simplified block diagram updated operation section text updated in applications information section updated figures 3, 5, 17, 18, 19, 20, 21, 22 updated package description table added package photo and updated related parts 1 2 2, 3, 4 5 6 7 8 9 10 through 20 13 through 24 25 28 d 3/12 added bga package option and mp temperature grade added bga package option, mp temperature grade, thermal resistance, and device weight updated note 2 clarified load transient response conditions updated recommended heat sinks table corrected mgn pin usage added package photo 1 2 4 5 20 24 30 (revision history begins at rev c)
ltm4616 30 4616fd linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax : (408) 434-0507 l www.linear.com ? linear technology corporation 2008 lt 0312 rev d ? printed in usa part number description comments ltc6908-2 resistor set oscillator with spread spectrum modulation tw o outputs 0/90, tsot-23 and 2mm 3mm dfn packages LTM4600 10a dc/dc module regulator basic 10a dc/dc module regulator, lga package LTM4600hvmp military plastic 10a dc/dc module regulator guaranteed operation from C55c to 125c ambient, lga package ltm4601/ ltm4601a 12a dc/dc module regulator with pll, output tracking/margining and remote sensing synchronizable, polyphase operation, ltm4601-1/ltm4601a-1 version has no remote sensing, lga package ltm4602 6a dc/dc module regulator pin compatible with the LTM4600, lga package ltm4603 6a dc/dc module regulator with pll and output tracking/margining and remote sensing synchronizable, polyphase operation, ltm4603-1 version has no remote sensing, pin compatible with the ltm4601, lga package ltm4604a low v in 4a dc/dc module regulator 2.375v v in 5.5v, 0.8v v out 5v, 9mm 15mm 2.32mm lga package ltm4608a low v in 8a dc/dc module regulator 2.7v v in 5.5v; 0.6v v out 5v; 9mm 15mm 2.82mm lga package ltm8022/ ltm8023 36v in , 1a and 2a dc/dc module regulator pin compatible; 4.5v v in 36v; 9mm 11.25mm 2.82mm lga package r elate d p arts p ackage p hoto

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